This invention relates to a header error correcting device for correcting a header error in ATM (asynchronous transfer mode) cells used in an STM (synchronous transfer mode) signal.
The ATM cells are transmitted in a synchronous transfer mode as the STM signal. The synchronous transfer mode is used on various levels. When transmitted in the synchronous transfer mode of a level M, where M represents a prescribed natural number, the STM signal is called an STM-M signal. An STM-1 signal is transmitted at a bit rate of 155.52 Mbits/s and comprises 2,016 telephone channels. An STM-4 signal is transmitted at a higher bit rate of 622.08 Mbits/s and comprises 8,064 telephone channels. An STM-16 signal is transmitted at a still higher bit rate of 2,488.32 Mbits/s and comprises 32,256 telephone channels.
In order to monitor the ATM cells used in the STM signal, a header error check (HEC) device is generally used. Such a header error check device has a data input terminal for receiving the STM signal comprising a header part. The header error check device is for checking a header error in the header part. The header part comprises first through P-th header blocks and a header error check block, where P represents a first predetermined natural number. Each of the header blocks comprises first through N-th ATM cell header units, where N represents a second predetermined natural number. The header error check block comprises first through N-th ATM cell header error check units. The first ATM cell header units of the first through the P-th header blocks and the first ATM cell header error check unit constitute a header of a first ATM cell. Likewise, the N-th ATM cell header units of the first through the P-th header blocks and the N-th ATM cell header error check unit constitute a header of an N-th ATM cell. Each of the first through the N-th ATM cell header units and the first through the N-th ATM cell header error check units comprises a third predetermined natural number of bits at a predetermined bit interval.
Thus, the STM signal is a time division multiplexed signal of the first through the N-th ATM cells. The second predetermined natural number N represents multiplicity of the time division multiplexed signal.
The header error check device includes a control signal producing section, such as an SDH (synchronous digital hierarchy) terminator or terminating circuit, connected to the data input terminal for producing an original unit control signal. In a conventional header error check device, the original unit control signal comprises first through N-th control signals. An n-th control signal is for indicating successively the bits of an n-th ATM cell header unit in each of the header blocks and the bits of an n-th header error check unit, where n is variable between 1 and N, both inclusive.
In the conventional header error check device, an n-th cyclic redundancy check (CRC) circuit is controlled by the n-th control signal to carry out cyclic redundancy check on each n-th ATM cell header unit of the STM signal. The n-th cyclic redundancy check circuit thereby checks the header error in the n-th ATM cell header units of the header blocks.
It is now understood that the conventional header error check device comprises first through N-th cyclic redundancy check circuits. As a consequence, the conventional header error check device is bulky and expensive.
In order to obtain a compact header error check device, an improved header error check device is proposed in a prior U.S. patent application Ser. No. 821,691 which was filed Jan. 16, 1992, under the title of "Compact device for monitoring ATM cells", by Hiroshi Yamasita and Takashi Miyazono for assignment to the present assignee. The above-named Takashi Miyazono is the instant applicant. The Miyazono et al patent application corresponds to a prior Canadian patent application No. 2,059,396 which was filed Jan. 15, 1992 and was filed on the basis of Japanese Patent Application No. 14963/1991 and others.
The improved header error check device comprises a sole error checking section connected to the data input terminal and to the control signal producing section for checking the header error in connection with an n-th ATM cell header unit of a p-th header block and an n-th ATM cell header error check unit when the original unit control signal indicates the n-th ATM cell header unit of the p-th header block and the n-th ATM cell header error check unit, where n is variable between 1 and N, both inclusive, p being variable between 1 and P, both inclusive.
The improved header error check device can check the header error in the header part of the STM signal. However, the improved header error check device can not correct the header error in the first through the N-th ATM cell header units of the first through the P-th header blocks of the STM signal.